1. Field of the Invention
The present invention relates to a standard cell layout for a LSI (large scale integrated circuit), and particularly to a large scale standard cell like a flip-flop standard cell (a so called bistable standard cell) whose length in the direction of the power source wire thereof can be controlled so as not to be larger than required.
2. Description of the Prior Art
A conventional standard cell used for a layout of a large scale integrated circuit, particularly a large scale cell like a flip-flop standard cell has a relatively long length in the direction of the power source wire thereof (hereinafter this direction is called the lateral direction) as compared with cells other than the flip-flop cell. Thus, when a circuit pattern is composed by combination of the flip-flop cell and others, a dead space tends to be produced in the circuit pattern owing to the uniformity of their lateral lengths. Accordingly, there is an inconvenience in the design of the circuit patterns composed by the combination.
FIG. 1 shows a composition of a conventional standard cell. As shown in the drawing, there are provided in the cell two power source wires 1, 1 extending substantially parallel to the lateral direction (X axis) of the cell so that a group of circuit elements such as transistors and diodes for composing a logical circuit are arranged in a space 2 defined between the two power source wires 1, 1.
Particularly, when flip-flop standard cells composed by the circuit elements as mentioned above are arranged in one cell row, the lateral length of the row becomes considerably large.
FIG. 2 shows a cell from which clock skew tends to occur, and FIG. 3 shows waveforms produced by clock skew shifting in timing from an original clock.
In FIG. 2, a driven clock is input to a circuit 20 comprising a plurality of cells respectively having a relatively long length and supplied by a clock signal i through a buffer 21. A clock signal (a) inputted to a cell A and a clock signal (b) inputted to a cell B are different from each other in their time constants determined by a wire resistance and a wire capacity between the buffer 21 and the cell A, and a wire resistance and capacity between the buffer 21 and the cell B.
Thus, as shown in FIG. 3, rise times of the original clock signal i, clock signal (a) inputted through Ri.sub.1 and Ci.sub.1, and clock signal (b) inputted via Ri.sub.2, Ci.sub.2, Ri.sub.3, and Ci.sub.3, shift from one another due to respective delays caused by the differences in the time constants. The shift is generally called clock skew. Accordingly, there has been desired a suitable layout of the cells to avoid then clock skew.
The clock line causing clock skew becomes long and large when flop-flop cells are scattered. Accordingly, if all the flip-flop cells are arranged in one cell row, it makes clock skew small. However, if the flip-flop cells are conventional ones, the following problems occur.
FIG. 4 shows an abstract layout of a portion of an IC composed of conventional cells, in which are shown a cell row including only flip-flop cells 3 and other cell rows including cells 4 other than flip-flop cells. As seen from the drawing, there are dead spaces 5 produced by the differences of the lateral lengths of the rows of the flip-flop cells. Accordingly, an area of the circuit pattern composed of the conventional cells by automatic placement and routing becomes larger than required.
Moreover, the conventional standard cell has only two power source wires 1, 1, thus it is impossible to connect cells inversely between the wires of the high potential side (V.sub.DD) and the low potential side (v.sub.SS) in one cell row.